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1 ? HFA1130 850mhz, output limiting, low distortion current feedback operational amplifier the HFA1130 is a high speed wideband current feedback amplifier featuring programmable output limits. built with intersil?s proprietary complementary bipolar uhf-1 process, it is the fastest monolithic amplifier available from any semiconductor manufacturer. this amplifier is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overdrive recovery times. the output limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. the sub-nanosecond overdrive recovery time quickly returns the amplifier to linear operation, following an overdrive condition. the HFA1130 offers significant performance improvements over the clc500/501/502. the op amps with fastest edges features ? user programmable output voltage limits ? low distortion (30mhz, hd2) . . . . . . . . . . . . . . . . -56dbc ? -3db bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 850mhz ? very fast slew rate . . . . . . . . . . . . . . . . . . . . . 2300v/ s ? fast settling time (0.1%). . . . . . . . . . . . . . . . . . . . . 11ns ? excellent gain flatness - (100mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.14db - (50mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.04db - (30mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.01db ? high output current . . . . . . . . . . . . . . . . . . . . . . . . . 60ma ? overdrive recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns applications ? residue amplifier ? video switching and routing ? pulse and video amplifiers ? wideband amplifiers ? rf/if signal processing ? flash a/d driver ? medical imaging systems ? related literature - an9420, current feedback theory - an9202, hfa11xx evaluation fixture pinout HFA1130 (soic) top view ordering information part number (brand) temp. range ( o c) package pkg. no. HFA1130ib (h1130i) -40 to 85 8 ld soic m8.15 hfa11xxeval dip evaluation board for high-speed op amps input 220mhz signal output (a v = 2) hfa113 0 op amp 0ns 25ns nc -in +in v- 1 2 3 4 8 7 6 5 v h v+ out v l - + data sheet july 2002 fn3369.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 absolute maximum ratings t a = 25 o c thermal information voltage between v+ and v-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v output current (50% duty cycle) . . . . . . . . . . . . . . . . . . . . . . 60ma operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) soic package . . . . . . . . . . . . . . . . . . . 170 n/a maximum junction temperature (plastic package) . . . . . . . 150 o c maximum storage temperature range . . . . .-65 o c to t a to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications v supply = 5v, a v = +1, r f = 510 ? , r l = 100 ? , unless otherwise specified parameter test conditions (note 2) test level temp. ( o c) min typ max units input characteristics input offset voltage (note 3) a 25 - 2 6 mv afull - - 10 mv input offset voltage drift c full - 10 - v/ o c v io cmrr ? v cm = 2v a 25 40 46 - db afull 38 - - db v io psrr ? v s = 1.25v a 25 45 50 - db afull 42 - - db non-inverting input bias current (note 3) +in = 0v a 25 - 25 40 a afull - - 65 a +i bias drift c full - 40 - na/ o c +i bias cms ? v cm = 2v a 25 - 20 40 a/v afull - - 50 a/v inverting input bias current (note 3) -in = 0v a 25 - 12 50 a afull - - 60 a -i bias drift c full - 40 - na/ o c -i bias cms ? v cm = 2v a 25 - 1 7 a/v afull - - 10 a/v -i bias pss ? v s = 1.25v a 25 - 6 15 a/v afull - - 27 a/v non-inverting input resistance a 25 25 50 - k ? inverting input resistance c 25 - 20 30 ? input capacitance (either input) b 25 - 2 - pf input common mode range c full 2.5 3.0 - v input noise voltage (note 3) 100khz b 25 - 4 - nv/ hz +input noise current (note 3) 100khz b 25 - 18 - pa/ hz -input noise current (note 3) 100khz b 25 - 21 - pa/ hz transfer characteristics a v = +2, unless otherwise specified open loop transimpedance (note 3) b 25 - 300 - k ? HFA1130
3 -3db bandwidth (note 3) v out = 0.2v p-p , a v = +1 b25530 850 - mhz -3db bandwidth v out = 0.2v p-p , a v = +2, r f = 360 ? b25 - 670 - mhz full power bandwidth 4v p-p , a v = -1 b full - 300 - mhz gain flatness (note 3) to 100mhz b 25 - 0.14 - db gain flatness to 50mhz b 25 - 0.04 - db gain flatness to 30mhz b 25 - 0.01 - db linear phase deviation (note 3) dc to 100mhz b 25 - 0.6 - degrees differential gain ntsc, r l = 75 ? b25 - 0.03 - % differential phase ntsc, r l = 75 ? b 25 - 0.05 - degrees minimum stable gain a full 1 - - v/v output characteristics a v = +2, unless otherwise specified output voltage (note 3) a v = -1 a 25 3.0 3.3 - v afull 2.5 3.0 - v output current r l = 50 ? , a v = -1 a 25, 85 50 60 - ma a -40 35 50 - ma dc closed loop output impedance (note 3) b25 - 0.07 - ? 2nd harmonic distortion (note 3) 30mhz, v out = 2v p-p b25 - -56 - dbc 3rd harmonic distortion (note 3) 30mhz, v out = 2v p-p b25 - -80 - dbc 3rd order intercept (note 3) 100mhz b 25 20 30 - dbm 1db compression 100mhz b 25 15 20 - dbm transient response a v = +2, unless otherwise specified rise time v out = 2.0v step b 25 - 900 - ps overshoot (note 3) v out = 2.0v step b 25 - 10 - % slew rate a v = +1, v out = 5v p-p b 25 - 1400 - v/ s a v = +2, v out = 5v p-p b 25 1850 2300 - v/ s 0.1% settling time (note 3) v out = 2v to 0v b 25 - 11 - ns 0.2% settling time (note 3) v out = 2v to 0v b 25 - 7 - ns power supply characteristics supply voltage range b full 4.5 - 5.5 v supply current (note 3) a 25 - 21 26 ma afull - - 33 ma limiting characteristics a v = +2, v h = +1v, v l = -1v, unless otherwise specified clamp accuracy v in = 2v, a v = -1 a 25 - 60 125 mv clamped overshoot v in = 1v, input t r /t f = 2ns b25 - 4 - % overdrive recovery time v in = 1v b 25 - 0.75 1.5 ns electrical specifications v supply = 5v, a v = +1, r f = 510 ? , r l = 100 ? , unless otherwise specified (continued) parameter test conditions (note 2) test level temp. ( o c) min typ max units HFA1130
4 application information optimum feedback resistor (r f ) the enclosed plots of inverting and non-inverting frequency response detail the performance of the HFA1130 in various gains. although the bandwidth dependency on a cl isn?t as severe as that of a voltage feedback amplifier, there is an appreciable decrease in bandwidth at higher gains. this decrease can be minimized by taking advantage of the current feedback amplifier?s unique relationship between bandwidth and r f . all current feedback amplifiers require a feedback resistor, even for unity gain applications, and the r f , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. thus, the amplifier?s bandwidth is inversely proportional to r f . the HFA1130 design is optimized for a 510 ? r f , at a gain of +1. decreasing r f in a unity gain application decreases stability, resulting in excessive peaking and overshoot (note: capacitive feedback causes the same problems due to the feedback impedance decrease at higher frequencies). at higher gains the amplifier is more stable, so r f can be decreased in a trade-off of stability for bandwidth. the table below lists recommended r f values for various gains, and the expected bandwidth. clamp operation general the HFA1130 features user programmable output clamps to limit output voltage excursions. clamping action is obtained by applying voltages to the v h and v l terminals (pins 8 and 5) of the amplifier. v h sets the upper output limit, while v l sets the lower clamp level. if the amplifier tries to drive the output above v h , or below v l , the clamp circuitry limits the output voltage at v h or v l ( the clamp accuracy), respectively. the low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or dacs. clamp circuitry figure 1 shows a simplified schematic of the HFA1130 input stage, and the high clamp (v h ) circuitry. as with all current feedback amplifiers, there is a unity gain buffer (q x1 - q x2 ) between the positive and negative inputs. this buffer forces -in to track +in, and sets up a slewing current of (v -in -v out )/r f . this current is mirrored onto the high impedance node (z) by q x3 -q x4 , where it is converted to a voltage and fed to the output via another unity gain buffer. if no clamping is utilized, the high impedance node may swing within the limits defined by q p4 and q n4 . note that when the output reaches it?s quiescent value, the current flowing through -in is reduced to only that small current (-i bias ) required to keep the output at the final voltage. tracing the path from v h to z illustrates the effect of the clamp voltage on the high impedance node. v h decreases by 2v be (q n6 and q p6 ) to set up the base voltage on q p5 . q p5 begins to conduct whenever the high impedance node negative clamp range b 25 - -5.0 to +2.0 - v positive clamp range b 25 - -2.0 to +5.0 - v clamp input bias current a 25 - 50 200 a clamp input bandwidth v h or v l = 100mv p-p b25 - 500 - mhz notes: 2. test level: a. production tested; b. typical or guaranteed limit based on characterization; c. design typical for information only. 3. see typical performance curves for more information. electrical specifications v supply = 5v, a v = +1, r f = 510 ? , r l = 100 ? , unless otherwise specified (continued) parameter test conditions (note 2) test level temp. ( o c) min typ max units a cl r f ( ? )bw (mhz) +1 510 850 -1 430 580 +2 360 670 +5 150 520 +10 180 240 +19 270 125 +1 +in v- v+ q p1 q n1 v- q n3 q p3 q p4 q n2 q p2 q n4 q p5 q n5 z v+ -in v out i clamp r f (external) q p6 q n6 v h r 1 50k (30k for v l ) 200 ? figure 1. HFA1130 simplified v h clamp circuitry HFA1130
5 reaches a voltage equal to q p5 ?s base + 2v be (q p5 and q n5 ). thus, q p5 clamps node z whenever z reaches v h . r 1 provides a pull-up network to ensure functionality with the clamp inputs floating. a similar description applies to the symmetrical low clamp circuitry controlled by v l . when the output is clamped, the negative input continues to source a slewing current (i clamp ) in an attempt to force the output to the quiescent voltage defined by the input. q p5 must sink this current while clamping, because the -in current is always mirrored onto the high impedance node. the clamping current is calculated as (v -in - v out )/r f . as an example, a unity gain circuit with v in = 2v, v h = 1v, and r f = 510 ? would have i clamp = (2-1)/510 ? = 1.96ma. note that i cc will increase by i clamp when the output is clamp limited. clamp accuracy the clamped output voltage will not be exactly equal to the voltage applied to v h or v l . offset errors, mostly due to v be mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. clamp accuracy is a function of the clamping conditions. referring again to figure 1, it can be seen that one component of clamp accuracy is the v be mismatch between the q x6 transistors, and the q x5 transistors. if the transistors always ran at the same current level there would be no v be mismatch, and no contribution to the inaccuracy. the q x6 transistors are biased at a constant current, but as described earlier, the current through q x5 is equivalent to i clamp . v be increases as i clamp increases, causing the clamped output voltage to increase as well. i clamp is a function of the overdrive level (v -in -v outclamped ) and r f , so clamp accuracy degrades as the overdrive increases, or as r f decreases. as an example, the specified accuracy of 60mv for a 2x overdrive with r f = 510 ? degrades to 220mv for r f = 240 ? at the same overdrive, or to 250mv for a 3x overdrive with r f = 510 ? . consideration must also be given to the fact that the clamp voltages have an effect on amplifier linearity. the ?nonlinearity near clamp voltage? curve in the data sheet illustrates the impact of several clamp levels on linearity. clamp range unlike some competitor devices, both v h and v l have usable ranges that cross 0v. while v h must be more positive than v l , both may be positive or negative, within the range restrictions indicated in the specifications. for example, the HFA1130 could be limited to ecl output levels by setting v h = -0.8v and v l = -1.8v. v h and v l may be connected to the same voltage (gnd for instance) but the result won?t be in a dc output voltage from an ac input signal. a 150 - 200mv ac si gnal will still be present at the output. recovery from overdrive the output voltage remains at the clamp level as long as the overdrive condition remains. when the input voltage drops below the overdrive level (v clamp /a vcl ) the amplifier will return to linear operation. a time delay, known as the overdrive recovery time, is required for this resumption of linear operation. the plots of ?unclamped performance? and ?clamped performance? highlight the HFA1130?s subnanosecond recovery time. the difference between the unclamped and clamped propagation delays is the overdrive recovery time. the appropriate propagation delays are 4.0ns for the unclamped pulse, and 4.8ns for the clamped (2x overdrive) pulse yielding an overdrive recovery time of 800ps. the measurement uses the 90% point of the output transition to ensure that linear operation has resumed. note: the propagation delay illustrated is dominated by the fixturing. the delta shown is accurate, but the true HFA1130 propagation delay is 500ps. use of die in hybrid applications this amplifier is designed with compensation to negate the package parasitics that typically lead to instab ilities. as a result, the use of die in hybrid applications results in overcompensated performance due to lower parasitic capacitances. reducing r f below the recommended values for packaged units will solve the problem. for a v = +2 the recommended starting point is 300 ? , while unity gain applications should try 400 ? . pc board layout the frequency performance of this amplifier depends a great deal on the amount of care taken in designing the pc board. the use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! attention should be given to decoupling the power supplies. a large value (10 f) tantalum in parallel with a small value chip (0.1 f) capacitor works well in most cases. terminated microstrip signal lines are recommended at the input and output of the device. output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the amplifier and may cause oscillations. in most cases, the oscillation can be avoided by placing a resistor in series with the output. care must also be taken to minimize the capacitance to ground seen by the amplifier?s inverting input. the larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. to this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should be kept as short as possible. an example of a good high frequency layout is the evaluation board shown below. HFA1130
6 evaluation board an evaluation board is available for the HFA1130, (part number hfa11xxeval). please contact your local sales office for information. note: the soic version may be evaluated in the dip board by using a soic-to-dip adapter such as aries electronics part number 08-350000-10. the layout and schematic of the board are shown here: 1 2 3 4 8 7 6 5 +5v 10 f 0.1 f v h 50 ? gnd gnd 500 ? 500 ? -5v 0.1 f 10 f 50 ? in out v l figure 2. board schematic v h +in v l v+ gnd 1 v- out top layout bottom layout typical performance curves v supply = 5v, r f = 510 ? , t a = 25 o c, r l = 100 ? , unless otherwise specified figure 3. small signal pulse response figure 4. large signal pulse response 120 time (5ns/div.) 90 60 30 0 -30 -60 -90 -120 output voltage (mv) a v = +2 time (5ns/div.) output voltage (v) 1.2 0.9 0.6 0.3 0 -0.3 -0.6 -0.9 -1.2 a v = +2 HFA1130
7 figure 5. unclamped performance figure 6. clamped performance figure 7. non-inverting frequency response figure 8. inverting frequency response figure 9. frequency response for various load resistors figure 10. frequency response for various load resistors typical performance curves v supply = 5v, r f = 510 ? , t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) in 0v to 0.5v out 0v to 1v time (10ns/div.) a v = +2, v h = 2v, v l = -2v in 0v to 1v out 0v to 1v time (10ns/div.) a v = +2, v h = 1v, v l = -1v, 2x overdrive frequency (mhz) 0 -3 -6 -9 -12 normalized gain (db) 0.3 1 10 100 1k 0 -90 -180 -270 -360 phase (degrees) phase gain a v = +11 a v = +1 a v = +6 a v = +11 a v = +1 a v = +6 a v = +2 a v = +2 v out = 200mv p-p frequency (mhz) phase gain 0 -3 -6 -9 -12 normalized gain (db) 0.3 1 10 100 1k 180 90 0 -90 -180 phase (degrees) a v = -5 a v = -1 a v = -10 a v = -20 a v = -20 a v = -10 a v = -5 a v = -1 v out = 200mv p-p frequency (mhz) 6 3 0 -3 -6 gain (db) 0.3 1 10 100 1k 0 -90 -180 -270 -360 phase (degrees) phase gain r l = 1k ? r l = 1k ? r l = 100 ? r l = 50 ? r l = 100 ? r l = 50 ? r l = 100 ? r l = 1k ? a v = +1, v out = 200mv p-p frequency (mhz) phase gain 3 0 -3 -6 normalized gain (db) 0.3 1 10 100 1k 0 -90 -180 -270 -360 phase (degrees) r l = 100 ? r l = 1k ? r l = 50 ? r l = 100 ? r l = 1k ? r l = 50 ? r l = 100 ? r l = 1k ? a v = +2, v out = 200mv p-p HFA1130
8 figure 11. frequency response for various output voltages figure 12. frequency response for various output voltages figure 13. frequency response for various output voltages figure 14. -3db bandwidth vs temperature figure 15. gain flatness figure 16. deviation from linear phase typical performance curves v supply = 5v, r f = 510 ? , t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) frequency (mhz) 20 10 0 -10 -20 gain (db) 0.3 1 10 100 1k -30 0.500v p-p 0.920v p-p 1.63v p-p 0.160v p-p a v = +1 frequency (mhz) 20 10 0 -10 -20 normalized gain (db) 0.3 1 10 100 1k -30 1.00v p-p 1.84v p-p 3.26v p-p 0.32v p-p a v = +2 frequency (mhz) 20 10 0 -10 -20 normalized gain (db) 0.3 1 10 100 1k -30 0.96v p-p 3.89v p-p to a v = +6 temperature ( o c) 950 900 850 800 750 bandwidth (mhz) -50 -25 0 75 125 700 25 50 100 a v = +1 frequency (mhz) 0 -0.05 -0.10 gain (db) 1 10 100 -0.15 -0.20 a v = +2 +2.0 +1.5 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 0 15 30 45 60 75 90 105 120 135 150 frequency (mhz) deviation (degrees) a v = +2 HFA1130
9 figure 17. open loop transimpedance figure 18. settling response figure 19. closed loop output resistance figure 20. 3rd order intermodulation intercept figure 21. 2nd harmonic distortion vs p out figure 22. 3rd harmonic distortion vs p out typical performance curves v supply = 5v, r f = 510 ? , t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) 250 25 2.5 0.25 0.01 0.1 1 10 100 500 180 135 90 45 0 phase (degrees) gain (k ? ) frequency (mhz) a v = -1 gain phase time (ns) 0.6 0.4 0.2 0 settling error (%) -4 1 6 21 31 -0.2 11 16 26 36 41 46 -0.4 -0.6 a v = +2, v out = 2v output resistance ( ? ) 1000 100 10 1 0.1 0.3 1 10 100 1000 frequency (mhz) frequency (mhz) 40 35 30 25 20 intercept point (dbm) 0100200 15 300 400 10 5 0 2-tone output power (dbm) -30 -35 -40 -45 -50 distortion (dbc) -5 3 -55 -60 -65 -70 -3 -1 1 5 7 9 11 13 15 100mhz 50mhz 30mhz output power (dbm) -30 -40 -50 -60 -70 distortion (dbc) -5 3 -80 -90 -100 -110 -3 -1 1 5 7 9 11 13 15 100mhz 50mhz 30mhz HFA1130
10 figure 23. overshoot vs input rise time figure 24. overshoot vs input rise time figure 25. overshoot vs feedback resistor figure 26. supply current vs temperature figure 27. supply current vs supply voltage figure 28. v io and bias currents vs temperature typical performance curves v supply = 5v, r f = 510 ? , t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) input rise time (ps) 38 36 34 32 30 overshoot (%) 100 500 28 26 24 22 200 300 400 600 700 800 900 1000 v out = 1v p-p v out = 2v p-p v out = 0.5v p-p 20 18 16 14 12 10 8 6 a v = +1 input rise time (ps) 35 30 25 20 15 overshoot (%) 100 500 10 5 0 200 300 400 600 700 800 900 1000 r f = 360 ? v out = 2v p-p r f = 510 ? v out = 0.5v p-p r f = 510 ? v out = 1v p-p r f = 360 ? v out = 1v p-p r f = 360 ? v out = 0.5v p-p r f = 510 ? v out = 2v p-p a v = +2 feedback resistor ( ? ) 36 34 32 30 overshoot (%) 360 520 28 26 24 22 400 440 480 560 600 640 680 20 18 16 14 12 10 8 6 4 a v = +2, t r = 200ps, v out = 2v p-p temperature ( o c) 25 24 23 22 21 supply current (ma) -60 20 20 19 18 -40 -20 0 40 60 80 100 120 total supply voltage (v+ - v-, v) 22 17 15 13 11 supply current (ma) 59 9 7 5 678 10 21 20 19 6 8 10 12 14 16 18 temperature ( o c) 45 42 39 36 33 bias currents ( a) -60 20 30 27 24 -40 -20 0 40 60 80 100 120 21 18 15 12 9 6 3 0 2.8 2.7 2.6 2.5 2.4 input offset voltage (mv) 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 +i bias v io -i bias HFA1130
11 figure 29. output voltage vs temperature figure 30. input noise vs frequency figure 31. non-linearity near clamp voltage typical performance curves v supply = 5v, r f = 510 ? , t a = 25 o c, r l = 100 ? , unless otherwise specified (continued) temperature ( o c) 3.7 3.6 3.5 3.4 output voltage (v) -60 20 3.3 3.2 3.1 3.0 -40 -20 0 40 60 80 100 2.9 2.8 2.7 2.6 2.5 120 | - v out | +v out (a v = -1, r l = 50 ? ) 300 275 250 225 200 175 150 125 100 75 50 25 0 30 25 20 15 10 5 0 100 1k 10k 100k frequency (hz) noise voltage (nv/ hz ) noise current (pa/ hz ) e ni i ni - i ni + 20 15 10 5 0 -5 -10 -15 -20 v out - (a v v in ) (mv) -3 -2 -1 0 1 2 3 a v v in (v) v l = -3v v l = -1v v l = -2v v h = 3v v h = 1v v h = 2v a v = -1, r l = 100 ? HFA1130
12 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com die characteristics metallization mask layout HFA1130 die dimensions: 63 mils x 44 mils x 19 mils 1600 m x 1130 m metallization: type: metal 1: alcu(2%)/tiw thickness: metal 1: 8k ? 0.4k ? type: metal 2: alcu(2%) thickness: metal 2: 16k ? 0.8k ? passivation: type: nitride thickness: 4k ? 0.5k ? transistor count: 52 substrate potential (powered up): floating (recommend connection to v-) +in v- v l bal out -in bal v h v+ HFA1130

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